module bidir(RW,data_bus,datain,dataout);
input RW;
inout [7:0 ]data_bus;
input [5:0]datain;	//swithes
output [7:0]dataout;
wire [7:0] buffer;

assign buffer [7:6] = {datain[5],datain[5]};
assign buffer [5:0] = datain [5:0];
assign data_bus = RW ? buffer : 1'bz;
assign dataout = data_bus ;


endmodule